Random notes for operating DBBC in the field
VSI connectors and data flow (Gino, email 20.01.2011)
What is received by the second Core2 in the 'vsi1' position is shifted by the second core2 in the
'vsi2' place.
Clock phase calibration on the Tunable firmware (Gino, email 20.01.2011)
There is a dbbc_config_file.txt with calibration setting. Here is reported. The goal of this calibration is to find the best phase relation between data and clock in the internal FPGA capture point. To do so a tone at an almost central frequency in the second Nyquist zone is injected and the 4 bbcs present in one Core2 are tuned equispaced in the entire band widh respect to this central tone. No bbc is tuned to see the tone. When things are correct the tone should not produce a contribution to the total power detected in all the 8 basebands 16 MHz wide (4U+4L). Indeed when phases are not correct spurious and additional components are generated and are visible in the bbcs' bands producing a total power contribution. Hope this could clarify the procedure.
Clock phases can be set manually with "f=<boardNr>,<phaseValue>". One channel may be viewed on the Analog Monitor output with "m=<boardNr>,<channelNr>" or "mon=<boardNr>,<channelNr>".
Modifying the phase of a board higher up in the stack will affect the spectrum of a monitor signal copied from farther down from the stack: Changing the phase in the Nth Core2 will change the phase relation you use to capture data from the monitor bus, with such consequences. Calibration is taking care of information produced and 'resident' only in the board under analysis, the total power. A more clever calibration process is anyway probably necessary.
