Field Notes

1. VSI connectors and data flow (Gino, email 20.01.2011)

What is received by the second Core2 in the 'vsi1' position is shifted by the second Core2 into the
'vsi2' place -- thus the output of the second Core2 will be {vsi1out:own data, vsi2out:previous board}

2. The agc_if tool

In the Polyphase firmware the agc_if tool modifies settings of IF A, B, C and D. Apparently agc_if can and should be run at the same time as test_poly16. The test_poly16 software does not configure the IF boards itself and neither does it report IF power levels.

To change IF A settings, choose 'a'. For editing IF B, choose 'b' and so on. Next you can change the signal input (example: 'a'->'i'->'2' to set IF A to use input #2), toggle the AGC on/off, choose the filter for the desired Nyquist zone (1=0..512, 2=512..1024, 3=1024..1536, example: 'a'->'l'->'2'), and set the AGC target value (example: 'a'->'c'->'22000).

In the Tunable firmware agc_if settings are overriden by the Control software. It seems both programs should never be run at the same time.

3. Clock phase calibration with the Polyphase firmware

A test tone at 764 MHz is injected to input 1 of all IF boards. Prior to calibration, use 'p' in the test_poly16 control program to list the total powers of all channels. Verify that channel #8 has maximum power and others are near zero. Start calibration with 'C'. It runs some minutes, output is logged into a log under C:\*.txt. Finally, a list of detected optimal phase values for each of the boards is printed. These values can be applied with "f=<boardNr>,<phaseValue>" and should also be copied into the C:\dbbc_conf\*.txt file.

Note: after 'C' completes all boards remain set to the last tested phase (255 255 255 255). Use a manual "f=..." or just restart test_poly16 to apply proper values.

4. Clock phase calibration with the Tunable firmware (Gino, email 20.01.2011)

"There is a dbbc_config_file.txt with calibration setting. Here is reported. The goal of this calibration is to find the best phase relation between data and clock in the internal FPGA capture point. To do so a tone at an almost central frequency in the second Nyquist zone is injected and the 4 bbcs present in one Core2 are tuned equispaced in the entire band widh respect to this central tone. No bbc is tuned to see the tone. When things are correct the tone should not produce a contribution to the total power detected in all the 8 basebands 16 MHz wide (4U+4L). Indeed when phases are not correct spurious and additional components are generated and are visible in the bbcs' bands producing a total power contribution. Hope this could clarify the procedure."

Clock phases can be set manually with "f=<boardNr>,<phaseValue>".

5. Analog Monitor output

One channel may be viewed on the Analog Monitor output with "m=<boardNr>,<channelNr>". For the Tunable firmware the syntax is "mon=<boardNr>,<channelNr>".

The monitor output can assist in clock phase tuning. However! Modifying the clock phase of one board will affect the spectrum of monitored 'earlier' boards.

"Changing the phase in the third Core2 will change the phase relation you use to capture data from the monitor bus, with such consequences. Calibration is taking care of information produced and 'resident' only in the board under analysis, the total power. A more clever calibration process is anyway probably necessary." (Gino, email 20.01.2011)

6. Mark5C and mode=...

Although Mark5C DRS 0.9 in Mark5B-mode does recognize channel bitmask commands such as mode=0x0000ffff:1; (or in FieldSystem: mk5b_mode/ext,0x0000ffff,1,1), the 5C will in reality ignore the bitmask and in any case records all channels. (Status of 01/2011)

7. 1PPS clock drift on Mark5B+

It has happened that a Mark5B+ connected via VSI to a DBBC will loose 1PPS sync. Even after a dot_set=:force; the 5B dotmon output signal will immediately and visibly drift away from the DBBC 1PPS Monitor signal. In some cases the problem disappears again for a longer time if DBBC electronics are power cycled.

The drift is due to a bad VSI data clock and may be due to two causes:
1) VSI connector not inserted properly, cleaning and re-seating should help. After a new dot_set=:force; you should see the 5B dotmon output stay in sync.
2) if the above did not help, yet power cycling the DBBC seems to fix the issue, the problem is likely a set of missing resistors on the FILA board. These are the 'enable' signals for the LVDS line drivers that drive the VSI cable. On a few FILA board the resistors were missing. Contact Michael Wunderlich for fixing.

8. Firmware configuration files C:\DBBC_CONF\*.txt

Tunable (DDC) example:

1 dbbc2.bit 684.99 16
1 dbbc2.bit 700.99 16
1 dbbc2.bit 716.99 16
1 dbbc2.bit 732.99 16
1 dbbc2.bit 134.99 16
1 dbbc2.bit 150.99 16
1 dbbc2.bit 166.99 16
1 dbbc2.bit 182.99 16
1 dbbc2.bit 597.00 16
1 dbbc2.bit 682.00 16
1 dbbc2.bit 853.00 16
1 dbbc2.bit 938.00 16
0 dbbc2.bit 597.00 16
0 dbbc2.bit 682.00 16
0 dbbc2.bit 853.00 16
0 dbbc2.bit 938.00 16
55000 55000 55000 55000
53 98 32 0
CAT1 1024

The first number in the tunable version is indicating whether the bbc is present or not. In the DBBC2 this works in groups of 4 (e.g. if you have bbc1 you'll have also 2--3-4 and so on).   This is necessary to the software to know the hardware configuration, number and address of boards to configure have a dialogue.   The tunable version still don't have this additional possibility to configure the Fila10G, as the polyphase has (even if still needs to be fixed).

Polyphase example:

0 poly_dbbc.bit
1 poly_dbbc.bit
2 poly_dbbc.bit
99 poly_dbbc.bit
99 ACE.bit
99 fila10g.bit
22000 22000 22000 22000
10 10 100 0
CAT2 1024

The first number instructs the test_poly16.exe program which firmware it should loaded onto which Core2 board. That number is not necessarily equal to the device index in the JTAG chain.

The last three rows configure the AGC target for each IF board ("22000 22000 22000 22000"), the inter-board clock vs data phase adjustment for ADC data ("10 10 100 0") and finally the version of the global clock synthesizer board and output frequency selection ("CAT2 1024").

9. VSI bits and channels

Polyphase firmware channel definition is the standard from Haystack (mark5 memo #016). In order:

ch0 (16MHz not usable)   pin 1 sign and 2 mag    VSI BS bit 0=s|1=m
ch1 32 MHz               pin 3 sign and 4 mag    VSI BS bit 2=s|3=m
ch2 32 MHz               pin 5 sign and 6 mag    VSI BS bit 4=s|5=m
..............................