Progress meeting 14.6.

-- Complete -----------------
Amit
RTC clock module ~done
SVN done
Wiki done
10G found

-- Other -----------------
10G computer setup todo
   - tcpdump ok
   - Rechenzentrum configures Myri driver+fw probably on 15.6.
Cabling mini-conn <=> VSI cable 
   - it's a board-specific adapter cable, may be available from Michael W.
   - Walter A. could bring the Metsähovi system to MPIfR @TOG visit
Mark5C network format
   - Gino worried about exactness, 10G NIC recording ok, should also verify Mark5C recording and net format
   - actually has optional 64-bit sequence number before VLBI payload
APEX
   - requires 32bit from one VSI, 2048 Mbps
   - fila10g should allow selecting (in SW/HW) between VSI1 and VSI2 as the source
Modified Julian Date
   - VLBA BCD Time code, surely identical to MJD 'JJJSSSSS' plus Year-since-2000 mentioned in all 
     Mark5B/5C data frame spec PDFs? 
Chet
   - sent 2 mails to Chet about Mk5C format + limitations + new experiences
 
-- Next -----------------
Next project meeting on Monday 21.6. (3pm?)
Contact Walter A. (Jan)
Send SVN intro (Jan)